A variety of integrated circuits comprise substantially parallel long lines coupling similar circuits. For example, many memory arrays comprise long bit lines coupling a plurality of memory cells in parallel that are physically close to one another. The physical characteristics of such lines, e.g., physical proximity and parallel layout, may lead to unwanted electrical coupling between and among such lines.
FIG. 1 (conventional art) illustrates an exemplary memory array 100, in accordance with the conventional art. Memory array 100 comprises a plurality of word lines, e.g., WL0 through WL255. Word line 170 (WL255) is one exemplary word line. Memory array 100 also comprises a plurality of bit lines, e.g., BL0 through BL255. Bit lines 110 (BL0) and 130 (BL1) are exemplary bit lines. Memory array 100 further comprises a plurality of inverted bit lines, e.g., BLB0 (“bit line bar”) through BLB255. Inverted bit lines 120 (BLB0) and 140 (BLB1) are exemplary inverted bit lines.
Located at the intersection of each word line and bit line is a memory cell, e.g., memory cell 150 and memory cell 160. In exemplary memory array 100, a cell (150, 160) may be considered to include both a bit line and an inverted bit line, although that is not required. In the case of exemplary memory array 100, a word line, e.g., word line 170 is asserted and the value of the plurality of memory cells is read on the bit lines, e.g., bit lines 110 and 130, and read on the inverted bit lines, e.g., inverted bit lines 120 and 140. For example, exemplary memory array 100 is illustrated to produce a b‘00’ as the first two bits of word line 170 (WL255). Similarly, exemplary memory array 100 stores b‘10’ as the first two bits of word line 180 (WL0).
It is to be appreciated that bit lines 110 and 130 and inverted bit lines 120 and 140 are not required to operate as binary signals, although that is possible. The bit lines and inverted bit lines may operate as differential pairs, with a signal value determined by a voltage difference between a bit line and inverted bit line of the same column. It is to be further appreciated that the voltage difference may have greater than a single bit of resolution, e.g., the single memory cell may store more than a single bit of information.
The discharge speed, and hence access time of a bit line is a function of the voltage and current waveforms on the bit line and/or inverted bit line, and in turn depends on the loading on the bit line and inverted bit line. The bit lines and inverted bit lines comprise long, parallel structures, and are susceptible to undesirable influences from one another, including, for example, capacitive coupling between a bit line and inverted bit line within a cell, e.g., 110 and 120, as well as coupling between lines of one cell and lines of a nearby cell, e.g., between inverted bit line 120 and bit line 130. Other factors, including, for example, ground bounce, may also unduly influence bit lines and/or inverted bit lines.
Unfortunately, such influences may cause a memory array to function undesirably slowly, e.g., to allow sufficient duration for such influences to settle, or cause disadvantageous erroneous operation, e.g., reading an incorrect value.